1. Field of the Invention
The present invention relates to a method and apparatus for driving a plasma display panel (PDP), and more particularly to a PDP driving method and apparatus for enhancing sustain discharge efficiency.
2. Description of the Background
Recently, flat panel displays, such as liquid crystal displays (LCDs), field emission displays (FEDs) and PDPs, have been actively developed. The PDPs may have higher luminance, higher luminous efficiency and a wider viewing angle. Therefore, they are considered as a primary substitute for conventional cathode ray tubes (CRTs) for large-screen displays of more than 40 inches.
Generally, the PDPs use plasma generated by gas discharge to display characters or images. They may include, according to their size, more than several thousands to millions of pixels arranged in a matrix format. PDPs may be classified into direct current (DC) and alternating current (AC) types according to their driving voltage waveforms and discharge cell structures.
The DC PDP has electrodes that are exposed in a discharge space, thereby causing current to directly flow through the discharge space when applying a voltage to the DC PDP. One of the disadvantages of the DC PDP is that it requires a resistor to limit this current. On the other hand, the AC PDP has electrodes covered with a dielectric layer that naturally forms a capacitance component to limit the current and protects the electrodes from ion impact during a discharge. Consequently, the AC PDP has a longer lifespan than the DC PDP.
FIG. 1 is a partial perspective view of a conventional AC PDP.
As shown in FIG. 1, scan electrodes 4 and sustain electrodes 5, which may be covered with a dielectric layer 2 and a protection film 3, are arranged in parallel pairs on a first glass substrate 1. A plurality of address electrodes 8, which are covered with an insulation layer 7, may be arranged on a second glass substrate 6. Barrier ribs 9 may be formed on the insulation layer 7 in parallel with, and in between, the address electrodes 8. A phosphor 10 may be coated on the surface of the insulation layer 7 and on both sides of the barrier ribs 9. The first and second glass substrates 1 and 6 face each other while defining a discharge space 11 therebetween so that the address electrodes 8 are orthogonal to the scan electrodes 4 and sustain electrodes 5. In the discharge space 11, discharge cells 12 are formed at intersections between the address electrodes 8 and the pairs of scan electrodes 4 and sustain electrodes 5, respectively.
FIG. 2 shows a typical electrode arrangement in the conventional PDP.
As shown in FIG. 2, the PDP's electrodes may be arranged in the form of an m×n matrix. In detail, address electrodes A1 to Am may be arranged in a column direction, and scan (Y) electrodes Y1 to Yn and sustain (X) electrodes X1 to Xn may be alternately arranged in a row direction. Discharge cells 12 shown in FIG. 2 correspond to the discharge cells 12 in FIG. 1.
FIG. 3 is a waveform diagram showing driving waveforms of a conventional PDP.
In a conventional PDP driving method, as shown in FIG. 3, one frame may be divided into a plurality of sub-fields, each of which may comprise a reset period, an address period and a sustain period.
In the reset period, wall charges formed by a previous sustain discharge are erased, and then wall charges are set up to stably perform a subsequent address discharge. In the address period, cells that are turned on and cells that are not turned on are selected, and wall charges accumulate on the turned-on cells (i.e., addressed cells). In the sustain period, a sustain discharge pulse is alternately applied to the X and Y electrodes to perform a sustain discharge to actually display an image on the addressed cells.
Here, the term “wall charges” refers to charges that are formed proximate to the electrodes on the wall (for example, dielectric layer) of the discharge cells and stored on the electrodes. The wall charges do not actually touch the electrodes themselves because the is dielectric layer covers the electrodes. However, for simplicity of description, the wall charges may be described herein as being “formed on”, “stored on” and/or “accumulated on” the electrodes.
When a moving image is provided on a frame-by-frame basis, a driving waveform is typically designed on the basis of a shortest-time frame because periods of respective frames of a signal inputted from a video processor may not be constant due to factors such as an image type, etc. Consequently, as FIG. 3 shows, an idle period may exist between frames.
Since the PDP generally has high power consumption due to its driving characteristics, a method for controlling power consumption, according to a load factor of a frame to be displayed, may be used. An auto power control (APC) operation has been proposed as such a power consumption control method. This method may reduce the number of sustain discharges when displaying a bright picture and increase the discharges when displaying a dark picture. Consequently, a long idle period may exist between a frame corresponding to a displayed bright picture and the next frame.
The idle period may be included between the sustain period of the last sub-field of the previous frame and the reset period of the first sub-field of the next frame, or in the sustain period of a frame's last sub-field. Therefore, in the idle period, voltages at the X and Y electrodes may be maintained in their last states of sustain discharge. That is, one of the X and Y electrodes may be maintained at a sustain discharge voltage, which is a high-level voltage, and the other is maintained at a low-level voltage. In the idle period of FIG. 3, a voltage of 0V is applied to the X electrode and a voltage of Vs is applied to the Y electrode.
A conventional PDP driving circuit, which generates a driving waveform, may include a reset driver for generating slowly rising and falling waveforms in the reset period, a scan driver for applying a scan pulse to the Y electrodes in the address period, and a sustain driver for generating a sustain discharge pulse in the sustain period.
Transistors may be formed as switches in the reset, scan and sustain drivers. A capacitor that is pre-charged with a desired voltage to supply the desired voltage may be provided in the reset and scan drivers. These capacitors (Cset and Csc, shown in FIG. 7) may be charged with the desired voltages through switches in the reset driver and scan driver, and slowly discharged when applying a sustain discharge voltage to the Y electrode.
A bootstrap capacitor may be formed in a voltage source of a circuit for driving each switch of each part. The bootstrap capacitor acts to supply a stable voltage.
FIG. 4 is a circuit diagram showing a conventional circuit for driving a switch FET.
As shown in FIG. 4, in order to drive the switch FET, a push-pull circuit including a bootstrap capacitor Cboot and transistors Q1 and Q2, connected to a gate control voltage source Vg, may be used. Turning the transistors Q1 and Q2 on/off drives the switch FET. The bootstrap capacitor Cboot is charged with a voltage Vcc, which may equal 15V, when the source voltage of the switch FET is low. The charged voltage is used to drive the switch FET. Here, the voltage source Vg is a bias voltage source for the transistors Q1 and Q2.
As mentioned above, the voltage Vs is applied to the Y electrode in the idle period. If the idle period is lengthened, the voltage Vs may be continuously applied to the source of the switch FET, so that the bootstrap capacitor Cboot discharges. Consequently, when the next frame starts, the transistors may not be normally driven, thereby causing lowered voltages to be charged in the capacitors Cset and Csc.
Therefore, a normal reset voltage or normal scan voltage may not be supplied. A large-capacitance capacitor, which increases a discharge time, may solve this problem, but this solution may not be desirable.